We're starting to learn a lot about Intel's upcoming next-gen Core-series processor, Haswell, and exactly what Intel means by a 'tock' release. When looking at the firm's charts, it feels as though the major breakthroughs will be taking place during a 'tick' release, when the architecture moves to a new, smaller fabrication process, much like Sandy Bridge to Ivy Bridge.
However, with the move to 22nm, we were perhaps thrown-off by the extra boost offered by 3D Transistors, which brought about more substantial performance-per-watt gains than a typical downsizing would bring. The truth is, Ivy Bridge is mostly just a smaller Sandy Bridge, with little changing and, it's Haswell or rather, the tock release, where the magic is going to happen.
In the tock stage, Intel takes its focus away from downsizing and brings it back to the design of the architecture. Haswell will be receiving a slurry of redesigns and improvements.
It's expected that the caching system will see an overhaul (more bandwidth, better predication), along with a larger, shared, Last Level Cache (LLC), which focuses on getting data onto the chip before deciding exactly which cores need it - the theory - that once one core has shown an interest in a dataset, often other cores will have a need for some level of access too and, managing concurrency is much faster on-die; the GPU is also expected to share this cache level, perhaps a sign of some serious GPGPU compute from Intel, certainly we're expecting many more GPU cores this time around.
New instructions and capabilities will be available for performing accelerated mathematics on multiple datasets - some of which we've seen implemented on the upcoming Xeon Phi - such as Scatter-gather, two Fused-Multiply-Add units, AVX2, endian conversion and bit-manipulation. New instructions will also be provided for hardware-accelerated locking of data, which when properly utilised, can offer performance superior to that of even fine-grain software locking of datasets - making it easier to keep cores either doing something useful as opposed to sat spinning in an active-lock state, or to place them to sleep sooner - this is a feature paired closely with the architecture's cache redesign.
Both the CPU and the chipset architecture will have a new focus on power efficiency, with more efficient sleep-states and with a Haswell chip utilising less power when routing interrupts, whilst the chipset witnesses a reduction to 32nm. Haswell is an architecture focused on Ultrabooks and tablet hybrids.
Most surprisingly, perhaps, is that Intel has revealed that despite being a tock release, Haswell will in fact feature a different type of transistor to the one in Ivy Bridge. Has the firm realised a design even more efficient (power, space?) than the 3D Transistors it last featured? Or perhaps has it found a design better capable of extreme overclocking? There were suggestions that Intel's move away from fluxless-solder to attach the heat-spreader could have been due to transistor fragility.
Either way, Haswell may be hiding an ace up its sleeve. Certainly, from the promises of more GPU cores and more cache, Haswell should be a large chip, however, with claims that it's the next big thing for Ultrabooks, Intel has clearly done some serious work on improving general efficiency.
