The JEDEC Solid State Technology Association has published an update to its High Bandwidth Memory (HBM) Standard. JEDEC's update to JESD235 High Bandwidth Memory (HBM) DRAM standard is called JESD235B (yes, the same but with a capital B suffix) and could bring noticeable performance benefits to upcoming HBM devices, be they designed for graphics, high performance computing (HPC), server, networking or client applications.
JEDEC worked with leading GPU and CPU developers to create JESD253B. It says that the new standard extends the system bandwidth growth curve for discrete packaged memory. The main boost for JESD253B is due to the leveraging of Wide I/O, alongside TSV technologies, and an improved per-pin bandwidth of 2.4Gbps.
Bandwidth is delivered across a 1024-bit bus, divided into 8 independent channels on each DRAM stack. Meanwhile the standard supports 2-high, 4-high, 8-high, and 12-high TSV (through-silicon via) stacks of DRAM at full bandwidth. As a result JESD253B HBM allows for flexible capacities from 1GB to 24GB per stack. With the extended per-pin bandwidth the total per-stack bandwidth is boosted beyond JESD253's 256GBps, up to 307GBps.
In summary, the new JESD253B revision HBM can produce devices up to 24GB with bandwidth up to 307GBps. At the time of writing none of the big memory makers have announced any JESD253B products, and the JEDEC press release doesn't share this type of industry intelligence. However, it wouldn't be surprising for one or more of the big memory makers to announce support soon, and high-end compute accelerator designers to announce products based upon this refreshed HBM.
